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74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 03 -- 21 May 2007 Product data sheet
1. General description
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
2. Features
s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V). 24 mA output drive (VCC = 3.0 V) ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V. CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C.
s s
s s s s s s
NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74LVC1G175GW 74LVC1G175GV 74LVC1G175GM 74LVC1G175GF -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C SC-88 SC-74 XSON6 XSON6 Description plastic surface-mounted package; 6 leads plastic surface-mounted package (TSOP6); 6 leads plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm Version SOT363 SOT457 SOT886 SOT891 Type number
4. Marking
Table 2. Marking Marking code YT V75 YT YT Type number 74LVC1G175GW 74LVC1G175GV 74LVC1G175GM 74LVC1G175GF
5. Functional diagram
6
3
MR D FF Q 4 CP
001aaa468
1 3 6
CP D MR
001aaa469
1
Q
4
Fig 1. Logic symbol.
Fig 2. IEC logic symbol.
CP
C C C C
Q
C D C MR
C
C
C
C
001aaa466
Fig 3. Logic diagram.
74LVC1G175_3 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 -- 21 May 2007
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
6. Pinning information
6.1 Pinning
74LVC1G175 74LVC1G175
CP GND 1 2 6 5 MR GND VCC D D 3
001aag506
CP
1
6
MR CP GND
74LVC1G175
1 2 3 6 5 4 MR VCC Q
2
5
VCC
3
4
Q
D
4
Q
001aag507
001aag508
Transparent top view
Transparent top view
Fig 4. Pin configuration SOT363 and SOT457
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
6.2 Pin description
Table 3. Symbol CP GND D Q VCC MR Pin description Pin 1 2 3 4 5 6 Description clock input (LOW-to-HIGH, edge-triggered) ground (0 V) data input flip-flop output supply voltage master reset input (active LOW)
7. Functional description
Table 4. Function table[1] Input MR Reset (clear) Load `1' Load `0'
[1]
Operating mode
Output CP X D X h l Q L H L
L H H
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; = LOW-to-HIGH CP transition; X = don't care.
74LVC1G175_3
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Product data sheet
Rev. 03 -- 21 May 2007
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Ptot Tstg
[1] [2] [3]
Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current total power dissipation storage temperature
Conditions VI < 0 V
[1]
Min -0.5 -50 -0.5 [1][2] [1][2]
Max +6.5 +6.5 50 VCC + 0.5 +6.5 50 100 250 +150
Unit V mA V mA V V mA mA mA mW C
VO > VCC or VO < 0 V Active mode Power-down mode VO = 0 V to VCC
-0.5 -0.5 -100
Tamb = -40 C to +125 C
[3]
-65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. For SC-88 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6. Symbol VCC VI VO Tamb t/V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Active mode Power-down mode; VCC = 0 V Conditions Min 1.65 0 0 0 -40 Typ Max 5.5 5.5 VCC 5.5 +125 20 10 Unit V V V V C ns/V ns/V
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Product data sheet
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
10. Static characteristics
Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +85 VIH C[1] VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOFF ICC ICC CI input leakage current power-off leakage current supply current additional supply current input capacitance VCC = 0 V to 5.5 V; VI = 5.5 V or GND VCC = 0 V; VI or VO = 5.5 V VCC = 1.65 V to 5.5 V; IO = 0 A; VI = 5.5 V or GND VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V; IO = 0 A VCC = 3.3 V; VI = GND to VCC
[2] [2]
Conditions
Min 0.65 x VCC 1.7 2.0 0.7 x VCC VCC - 0.1 1.2 1.9 2.2 2.3 3.8 -
Typ 1.54 2.15 2.50 2.62 4.11 0.07 0.12 0.17 0.33 0.39 0.1 0.1 0.1 5 2.5
Max 0.35 x VCC 0.7 0.8 0.3 x VCC 0.10 0.45 0.30 0.40 0.55 0.55 5 10 10 500 -
Unit V V V V V V V V V V V V V V V V V V V V A A A A pF
HIGH-level input voltage
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Product data sheet
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74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Table 7. Static characteristics ...continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +125 C VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOFF ICC ICC input leakage current power-off leakage current supply current additional supply current VCC = 0 V to 5.5 V; VI = 5.5 V or GND VCC = 0 V; VI or VO = 5.5 V VCC = 1.65 V to 5.5 V; IO = 0 A; VI = 5.5 V or GND VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V; IO = 0 A 0.10 0.70 0.45 0.60 0.80 0.80 20 20 40 5000 V V V V V V A A A A VCC - 0.1 0.95 1.7 1.9 2.0 3.4 V V V V V V 0.65 x VCC 1.7 2.0 0.7 x VCC 0.35 x VCC 0.7 0.8 0.3 x VCC V V V V V V V V Conditions Min Typ Max Unit
[1] [2]
All typical values are measured at Tamb = 25 C. These typical values are measured at VCC = 3.3 V.
74LVC1G175_3
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Product data sheet
Rev. 03 -- 21 May 2007
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
11. Dynamic characteristics
Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter tpd Conditions -40 C to +85 C Min propagation delay CP to Q; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V MR to Q; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW pulse width CP HIGH or LOW; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V MR LOW; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V trec recovery time MR; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tsu set-up time D to CP; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
74LVC1G175_3
-40 C to +125 C Unit Min 1.5 1.0 1.0 0.5 0.5 1.5 1.0 1.0 0.5 0.5 Max 17 9.0 9.0 7.5 5.5 17 9.0 9.0 7.5 5.5 ns ns ns ns ns ns ns ns ns ns
Typ[1] 4.9 3.1 3.2 3.1 2.2 4.3 2.8 3.0 2.5 2.0
Max 13.4 7.1 7.1 5.7 4.0 12.9 7.0 7.0 5.8 4.1
1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0
6.2 2.7 2.7 2.7 2.0 6.2 2.7 2.7 2.7 2.0 1.9 1.4 1.3 1.2 1.0 2.9 1.7 1.7 1.3 1.1
1.3 1.6 0.4 0.5 -
-
6.2 2.7 2.7 2.7 2.0 6.2 2.7 2.7 2.7 2.0 1.9 1.4 1.3 1.2 1.0 2.9 1.7 1.7 1.3 1.1
-
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Product data sheet
Rev. 03 -- 21 May 2007
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter th hold time Conditions D to CP; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum frequency CP; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance VI = GND to VCC; VCC = 3.3 V
[3]
-40 C to +85 C Min 0.0 0.3 0.5 1.2 0.5 80 175 175 175 200 Typ[1] 0.2 125 300 14 Max -
-40 C to +125 C Unit Min 0.0 0.3 0.5 1.2 0.5 80 175 175 175 200 Max ns ns ns ns ns MHz MHz MHz MHz MHz pF
[1] [2] [3]
Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs.
74LVC1G175_3
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Product data sheet
Rev. 03 -- 21 May 2007
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
12. Waveforms
VI D input GND th tsu 1/fmax VI CP input GND tW tPHL VOH Q output VOL VM
001aaa465
VM
th tsu
VM
tPLH
Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to D hold times, and the maximum clock pulse frequency
VI MR input GND tW VI CP input GND t PHL VOH Q output VOL VM
001aaa464
VM
t rec
VM
Measurement points are given in Table 9. VOL and VOH are typical output voltage drops that occur with the output load.
Fig 8. The master reset (MR) input to output (Q) propagation delays, the master reset pulse width, and the MR to CP recovery time
74LVC1G175_3
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Product data sheet
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74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Table 9. VCC
Measurement points Input VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC Output VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC
Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V
VEXT VCC PULSE GENERATOR VI DUT
RT CL RL RL
VO
mna616
Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.
Fig 9. Load circuitry for switching times Table 10. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr = t f 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 k 500 500 500 500 VEXT tPLH, tPHL open open open open open
Supply voltage
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Product data sheet
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
13. Package outline
Plastic surface-mounted package; 6 leads SOT363
D
B
E
A
X
y
HE
vMA
6
5
4
Q
pin 1 index
A
A1
1
e1 e
2
bp
3
wM B detail X Lp
c
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT363
REFERENCES IEC JEDEC JEITA SC-88
EUROPEAN PROJECTION
ISSUE DATE 04-11-08 06-03-16
Fig 10. Package outline SOT363 (SC-88)
74LVC1G175_3 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 -- 21 May 2007
11 of 17
NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Plastic surface-mounted package (TSOP6); 6 leads
SOT457
D
B
E
A
X
y
HE
vMA
6
5
4
Q
pin 1 index
A A1 c
1
2
3
Lp
e
bp
wM B detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.1 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT457
REFERENCES IEC JEDEC JEITA SC-74
EUROPEAN PROJECTION
ISSUE DATE 05-11-07 06-03-16
Fig 11. Package outline SOT457 (SC-74)
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Product data sheet
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b 1 2 3 4x L1 L
(2)
e
6 e1
5 e1
4
6x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22
Fig 12. Package outline SOT886 (XSON6)
74LVC1G175_3 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 -- 21 May 2007
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
1
2
b 3 4x
(1)
L1 e
L
6 e1
5 e1
4
6x
(1)
A
A1 D
E
terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm
Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15
Fig 13. Package outline SOT891 (XSON6)
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Product data sheet
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74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
14. Abbreviations
Table 11. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
15. Revision history
Table 12. Revision history Release date 20070521 Data sheet status Product data sheet Change notice Supersedes 74LVC1G175_2 Document ID 74LVC1G175_3 Modifications:
* * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74LVC1G175GF (XSON6/SOT891 package) Section 10 "Static characteristics": Changed: Conditions for input leakage and supply current. Product specification Product specification 74LVC1G175_1 -
74LVC1G175_2 74LVC1G175_1
20041018 20040318
74LVC1G175_3
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Product data sheet
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74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC1G175_3
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 -- 21 May 2007
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74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
18. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 May 2007 Document identifier: 74LVC1G175_3

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